Edge connect wafer level stacking

ABSTRACT

In accordance with an aspect of the invention, a stacked microelectronic package is provided which may include a plurality of subassemblies, e.g., a first subassembly and a second subassembly underlying the first subassembly. A front face of the second subassembly may confront the rear face of the first subassembly. Each of the first and second subassemblies may include a plurality of front contacts exposed at the front face, at least one edge and a plurality of front traces extending about the respective at least one edge. The second subassembly may have a plurality of rear contacts exposed at the rear face. The second subassembly may also have a plurality of rear traces extending from the rear contacts about the at least one edge. The rear traces may extend to at least some of the plurality of front contacts of at least one of the first or second subassemblies.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation-in-part of U.S. application Ser. No. 11/704,713 filed Feb. 9, 2007. Said application Ser. No. 11/704,713 claims the benefit of the filing date of U.S. Provisional Patent Application No. 60/850,850 filed Oct. 10, 2006. The disclosures of said applications are hereby incorporated herein by reference.

BACKGROUND OF THE INVENTION

The present invention generally relates to stacked microelectronic packages including stacked microelectronic packages fabricated at the wafer level and to methods of making such packages.

Semiconductor chips are flat bodies with contacts disposed on the front surface that are connected to the internal electrical circuitry of the chip itself.

Semiconductor chips are typically packaged with substrates to form microelectronic packages having terminals that are electrically connected to the chip contacts. The package may then be connected to test equipment to determine whether the packaged device conforms to a desired performance standard. Once tested, the package may be connected to a larger circuit, e.g., a circuit in an electronic product such as a computer or a cell phone.

The substrate materials used for packaging semiconductor chips are selected for their compatibility with the processes used to form the packages. For example, during solder or other bonding operations, intense heat may be applied to the substrate. Accordingly, metal lead frames have been used as substrates. Laminate substrates have also been used to package microelectronic devices. Such substrates may include two to four alternating layers of fiberglass and epoxy, wherein successive fiberglass layers may be laid in traversing, e.g., orthogonal, directions. Optionally, heat resistive compounds such as bismaleimide triazine (BT) may be added to such laminate substrates.

Tapes have been used as substrates to provide thinner microelectronic packages. Such tapes are typically provided in the form of sheets or rolls of sheets. For example, single and double sided sheets of copper-on-polyimide are commonly used. Polyimide based films offer good thermal and chemical stability and a low dielectric constant, while copper having high tensile strength, ductility, and flexure has been advantageously used in both flexible circuit and chip scale packaging applications. However, such tapes are relatively expensive, particularly as compared to lead frames and laminate substrates.

Microelectronic packages also include wafer level packages, which provide a package for a semiconductor component that is fabricated while the die are still in a wafer form. The wafer is subject to a number of additional process steps to form the package structure and the wafer is then diced to free the individual die. Wafer level processing may provide a cost savings advantage. Furthermore, the package footprint can be identical to the die size, resulting in very efficient utilization of area on a printed circuit board (PCB) to which the die will eventually be attached. As a result of these features, die packaged in this manner are commonly referred to as wafer level chip scale package (WLCSP).

In order to save space certain conventional designs have stacked multiple microelectronic chips within a package. This allows the package to occupy a surface area on a substrate that is less than the total surface area of the chips in the stack. However, conventional stacked packages have disadvantages of complexity, cost, thickness and testability.

In spite of the above advances, there remains a need for improved wafer-scale packages and especially stacked wafer-scale packages that are reliable, thin, testable and that are economical to manufacture.

SUMMARY OF THE INVENTION

The present invention provides apparatus and methods for production of integrated circuit devices to create stacked microelectronic packages suitable for processing at a wafer level to produce integrated circuits of lower cost, smaller size, lower weight, enhanced electrical performance.

In accordance with a preferred embodiment of the present invention, a method for producing integrated circuit devices is provided including the steps of forming a microelectronic assembly by stacking a first subassembly including a plurality of microelectronic elements onto a second subassembly including a plurality of microelectronic elements, wherein the microelectronic elements have traces extending to their edges, then forming notches partway through the microelectronic assembly so as to expose the traces and subsequently forming leads at the sidewalls of the notches to provide electrical contacts on a planar surface of the assembly. Subsequently, the assembly is diced in order to form individual electronic elements in accordance with the preferred embodiment of the present invention. The step of forming notches extends only partway through the at least one subassembly allows continued wafer-level processing of the elements.

In an additional embodiment of the present invention, the stacked assemblies incorporate a substrate to provide additional mechanical integrity to the assembly both during and after processing. The substrate may incorporate relief cavities that reduce stress concentrations during the notching process. It has been found that without such cavities, there is a propensity for the substrate to crack during the notching process.

In another aspect of the invention, adhesives are used to laminate the various layers of microelectronic sub-assemblies. Because of the stacking method, the traces of each subassembly are supported and retained by the adhesive of the immediate layer below and thereby prevented from being damaged.

In a still further preferred embodiment of the invention, each layer is initially notched to expose the traces and then filled with adhesive during the laminating process and this pattern of notching and filling is repeated for each of the subassembly layers. In this manner, when the notching occurs that will differentiate the microelectronic elements, the notching occurs entirely through the adhesive layers and the traces so that the traces are mechanically supported and insulated by the adhesive during the notching process.

It is a further aspect to the invention that the initial notching process is performed by non-mechanical means such as etching in order to preserve the mechanical integrity of the traces so that they remain intact.

It is an additional aspect of the present invention that stacked microelectronic packages comprising four subassembly layers and a substrate layer may have an overall package thickness of no more than 155 micrometers and that this thickness may be reduced by reducing the thickness of the substrate to a stacked thickness of no more than 125 micrometers.

In another embodiment of the invention, the stacked electronic packages have traces formed to both the top and bottom surfaces so that the stacked packages may be in turn stacked because the respective contacts on top and bottom layers of the packing can be aligned.

In a further preferred embodiment of the invention a method of making a stacked microelectronic package includes the steps of a) forming a microelectronic assembly by stacking a first subassembly including a plurality of microelectronic elements onto a substrate, stacking a second subassembly including a plurality of microelectronic elements onto the first subassembly, at least some of the plurality of microelectronic elements of the first subassembly and the second subassembly having traces that extend to respective edges of the microelectronic elements; b) forming notches in the microelectronic assembly so as to expose the traces of at least some of the plurality of microelectronic elements; and c) forming leads at the side walls of the notches, the leads being in electrical communication with at least some of the traces. In a further aspect of this embodiment the step of forming notches optionally includes forming initial notches in at least the first subassembly so as to expose the traces and filling the initial notches with adhesive so as to cover the traces and forming initial notches in at least the second subassembly so as to expose the traces and filling the initial notches with adhesive so as to cover the traces and forming the notches in the adhesive so as to expose the traces of at least some of the plurality of microelectronic elements.

An addition embodiment of the invention includes a method of making a microelectronic subassembly including the steps of a) forming initial notches in a first subassembly, including a plurality of microelectronic elements, the subassembly having traces that extend to respective edges of the microelectronic elements, so as to expose the traces; b) filling the initial notches with adhesive so as to cover the traces; and c) forming notches in the adhesive so as to expose the traces of at least some of the plurality of microelectronic elements.

An additional embodiment of the invention is a stacked microelectronic package including four subassemblies and a substrate stacked to each other, each subassembly including at least one microelectronic chip where the package has a stack thickness of no more than 155 micrometers. Such a package without a substrate has a stack thickness of no more than 125 micrometers.

An additional preferred embodiment of the invention is a method of making a stacked microelectronic package including the steps of a) forming a microelectronic assembly by stacking a first subassembly including a plurality of microelectronic elements onto the adhesive layer of a substrate, at least some of the plurality of microelectronic elements of the first subassembly having traces that extend to respective edges of the microelectronic elements; and then b) forming initial notches in the first subassembly so as to expose the traces and coating an adhesive layer on the first subassembly so as to fill the initial notches with adhesive and cover the traces; and then c) stacking a second subassembly including a plurality of microelectronic elements onto the adhesive layer of the first subassembly, at least some of the plurality of microelectronic elements of the first subassembly having traces that extend to respective edges of the microelectronic elements; and then d) forming initial notches in the second subassembly so as to expose the traces and coating an adhesive layer on the second subassembly so as to fill the initial notches with adhesive and cover said traces; and then e) forming notches in the adhesive layers so as to expose the traces of at least some of the plurality of microelectronic elements; and f) forming leads at the side walls of the notches, the leads being in electrical communication with at least some of the traces.

In one embodiment of the invention, a method is provided for manufacturing a stacked package. In such method, the saw lanes of a first wafer can be aligned with saw lanes of a second wafer such that the saw lanes of one wafer are positioned above the saw lanes of the other wafer. Each of the first and second wafers may include a plurality of microelectronic elements attached together at the saw lanes. Each microelectronic element may also have a plurality of traces extending toward the saw lanes. A plurality of openings can be formed which are aligned with the saw lanes of the first wafer and the second wafer. Each opening may expose a single trace of at least one microelectronic element. Leads can then be electrically connected with at least some of the exposed plurality of traces.

Each opening may expose a single trace of a microelectronic element of the first wafer. The same opening may also expose a single trace of a microelectronic element of the second wafer. Each opening may expose a single trace of more than microelectronic elements of the first wafer. The same opening may also expose a single trace of one or more than one microelectronic elements of the second wafer.

In one embodiment, the first wafer may be attached to the second wafer after the saw lanes of the two wafers are aligned.

In one embodiment, the leads may include first ends which overlie a face of one of the first and the second wafers. The first ends of the leads may include conductive bumps.

In one embodiment, The first and second wafers may be severed along the saw lanes into a plurality of assemblies, where each assembly includes a plurality of stacked microelectronic elements and exposed leads.

The saw lanes of at least one additional wafer including a plurality of additional microelectronic elements may be attached together at the saw lanes with the saw lanes of the first and second wafers.

The plurality of microelectronic elements may have additional traces which extend towards the saw lanes. Single ones of the additional traces of at least one of the additional microelectronic elements may be exposed during the step of forming the openings.

In accordance with an aspect of the invention, a stacked microelectronic assembly is provided which includes a first stacked subassembly and a second stacked subassembly overlying a portion of the first stacked subassembly. Each stacked subassembly may include a first microelectronic element having a face. A second microelectronic element having a face may overlie and be parallel to the face of the first microelectronic element. Each of the first and second microelectronic elements may have edges extending away from the respective face. A plurality of traces at the respective face may extend about at least one respective edge. Each of the first and second stacked subassemblies may include contacts connected to at least some of the plurality of traces. Bond wires may conductively connect the contacts of the first stacked subassembly with the contacts of the second stacked subassembly.

In one embodiment, each of the first and second subassemblies may have a face, and at least some of the plurality of contacts be exposed at least one of the faces of the first and second subassemblies.

Each of the first and second stacked subassemblies may have a face and an edge extending away from the face. The face of the first stacked subassembly may extend beyond the face of the second stacked subassembly such that contacts at the face of the first stacked subassembly are exposed beyond the face of the second stacked subassembly.

In accordance with an aspect of the invention, a stacked microelectronic package is provided which may include a plurality of subassemblies, e.g., a first subassembly and a second subassembly underlying the first subassembly. Each subassembly may have a front face and a rear face remote from the front face. The front face of the second subassembly may confront the rear face of the first subassembly. Each of the first and second subassemblies may include a plurality of front contacts exposed at the front face, at least one edge and a plurality of front traces extending about the respective at least one edge. The second subassembly may have a plurality of rear contacts exposed at the rear face. The second subassembly may also have a plurality of rear traces extending from the rear contacts about the at least one edge. The rear traces may extend to at least some of the plurality of front contacts of at least one of the first or second subassemblies.

In one embodiment, each of the plurality of subassemblies includes at least one microelectronic chip. An assembly including the microelectronic package may further include a circuit panel having terminals conductively connected to at least some package contacts, e.g., selected from the group consisting of the rear contacts of the second subassembly and front contacts of one subassembly of the plurality of subassemblies.

An additional microelectronic chip can be joined to the stacked microelectronic package or assembly. In one embodiment, a face of the additional microelectronic chip confronts a face of one of the first and second subassemblies. The assembly may further include bond wires which conductively connect contacts of the additional microelectronic chip to the terminals of the circuit panel.

Contacts of the additional microelectronic chip may be wire-bonded to the front contacts of the one subassembly. Conductive masses may join the contacts of the additional microelectronic chip to the front contacts of the one subassembly.

In one embodiment, the additional microelectronic chip may include a microcontroller.

In one embodiment, one or more microelectronic chips in the plurality of subassemblies may be replaceable by the additional microelectronic chip. For example, a microelectronic chip of the assembly can be replaced by disconnecting the microelectronic chip from ones of the front contacts of one subassembly and then connecting the additional microelectronic chip to the ones of the front contacts.

The assembly may further include bond wires which conductively connect the front contacts of the one subassembly to the terminals of the circuit panel.

In one embodiment, conductive masses may join the contacts of the additional microelectronic chip to the front contacts of the one subassembly.

In one embodiment, conductive masses may join the terminals of the circuit panel to the exposed front contacts of the one subassembly.

An additional microelectronic chip may be joined to the rear face of the second subassembly. In such assembly, the additional microelectronic chip may have contacts conductively connected to terminals of the circuit panel.

Bond wires may join the contacts of the additional microelectronic chip to the terminals of the circuit panel.

In one embodiment, conductive masses may join the terminals of the circuit panel to the rear contacts of the second subassembly.

In an embodiment, an additional microelectronic chip may have contacts in conductive communication with the front contacts of the one subassembly.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a top view of a subassembly according to one embodiment of the present invention;

FIG. 1B is a cross-sectional view of the subassembly of FIG. 1A;

FIG. 2 is a cross-sectional view of a plurality of subassemblies attached to one another to form a stacked assembly;

FIG. 3 is a cross-sectional view of the stacked assembly of FIG. 2 at a later stage during a method of manufacture according to one embodiment of the present invention;

FIG. 4A is a cross-sectional view of the stacked assembly of FIG. 3 at a later stage of manufacture according to one embodiment of the present invention;

FIG. 4B is a cross-sectional blown-up view of a portion of the stacked assembly of FIG. 4A.

FIG. 5 is a cross-sectional view of the stacked assembly of FIG. 4A after the stacked assembly has been diced into individual units;

FIG. 6 is a cross-sectional view of an alternate embodiment of a stacked assembly according to an embodiment of the present invention; and

FIG. 7A is a top view of a subassembly according to one embodiment of the present invention;

FIG. 7B is a cross-sectional view of the subassembly of FIG. 7A.

FIG. 7C is a bottom-view of the subassembly of FIG. 1A;

FIG. 8 is a cross-sectional view of a substrate used in an additional embodiment of the invention using a substrate to form a stacked assembly;

FIG. 9 is a cross-sectional view of the substrate of FIG. 8 at a later stage during a method of manufacture according to one embodiment in the present invention;

FIG. 10 is a cross-sectional view of the substrate of FIG. 9 at a later stage during the method of manufacture according to one embodiment of the present invention;

FIG. 11 is a cross-sectional view of a stacked assembly wherein the subassembly of FIG. 7A-C is stacked on top of a substrate of FIG. 10 during a later stage of manufacture according to one embodiment of the present invention;

FIG. 12 is a cross-sectional view of the stacked assembly of FIG. 11 at a later stage during a method of manufacture according to one embodiment of the present invention;

FIG. 13 is a cross-sectional view of the stacked assembly of FIG. 12 at a later stage during a method of manufacture according to one embodiment of the present invention;

FIG. 14 is a cross-sectional view of the stacked assembly of FIG. 13 at a later stage during a method of manufacture according to one embodiment of the present invention;

FIG. 15 is a cross-sectional view of the stacked assembly of FIG. 14 at a later stage during a method of manufacture according to one embodiment of the present invention;

FIG. 16 is a cross-sectional view of the stacked assembly of FIG. 15 at a later stage during a method of manufacture according to one embodiment of the present invention;

FIG. 17 is a cross-sectional view of the stacked assembly of FIG. 16 at a later stage during a method of manufacture according to one embodiment of the present invention;

FIG. 18 is a cross-sectional view of the stacked assembly of FIG. 17 at a later stage during a method of manufacture according to one embodiment of the present invention;

FIG. 19 is a cross-sectional view of the stacked assembly of FIG. 18 at a later stage during a method of manufacture according to one embodiment of the present invention;

FIG. 20 is a cross-sectional view of an alternative embodiment of a stacked assembly based on the assembly shown in FIG. 19;

FIG. 20A is a sectional view illustrating a stacked microelectronic assembly in which individual stacked assemblies are further stacked one on top of the other and conductively connected to each other

FIG. 21 is a cross-sectional view of the stacked assembly of FIG. 19 after the stacked assembly has been diced into individual units;

FIG. 22 is a cross-sectional view of an individual element created by the dicing process of FIG. 21 configured for wire bonding;

FIG. 23 is a cross-sectional view of an individual element according to FIG. 21 configured for bonding using a solder ball.

FIG. 24 is a bottom view of a variation of the stacked assembly illustrated in FIG. 21.

FIGS. 25A and 25B are illustrations of apparatus typically employed in the manufacture of stacked assemblies discussed herein.

FIG. 26 is a sectional view of a stacked assembly as attached to a circuit panel in accordance with an embodiment of the invention.

FIG. 27 is a sectional view of a stacked assembly as attached to a circuit panel in accordance with a variation of the embodiment illustrated in FIG. 26.

FIG. 28 is a sectional view of a stacked assembly as attached to a circuit panel in accordance with another variation of the embodiment illustrated in FIG. 26.

FIG. 29 is a sectional view of a stacked assembly as attached to a circuit panel in accordance with another embodiment of the invention.

FIG. 30 is a sectional view of a stacked assembly as attached to a circuit panel in accordance with a variation of the embodiment illustrated in FIG. 29.

FIG. 31 is a sectional view of a stacked assembly as attached to a circuit panel in accordance with another variation of the embodiment illustrated in FIG. 29.

FIG. 32 is a sectional view of a stacked assembly as attached to a circuit panel in accordance with another embodiment of the invention.

DETAILED DESCRIPTION

Reference is now made to FIGS. 1-4B, which illustrate a method and apparatus for stacking microelectronic components. As shown in FIGS. 1A-1B, a portion of a first wafer or subassembly 10 includes a plurality of microelectronic elements 12, each positioned side by side and adjacent to one another. The first wafer or subassembly 10 preferably includes numerous rows of microelectronic elements 12 aligned along an X-axis and a Y-axis. The microelectronic elements are formed integral with one another using conventional semiconductor process techniques. It should be apparent that the subassembly 10 may be a portion of a wafer. And the broken lines in the FIG. 1A illustrate that the subassembly may have additional elements attached thereto and may be in the shape of a circular wafer.

Each microelectronic element 12 includes a front face 14 and an oppositely-facing rear face 16. The microelectronic elements 12 also include first edges 18, second edges 20, third edges 19 and fourth edges 21, all of which extend from the front faces 14 to the rear faces 16 of the microelectronic elements 12. As shown in FIGS. 1A-1B, a first edge 18 of one microelectronic element 12 is attached to a second edge 20 of a second and adjacent microelectronic element 12. Similarly, a third edge 19 of one microelectronic element 12 is attached to a fourth edge 21 of an adjacent microelectronic element. Thus, the microelectronic elements 12 positioned within the middle of the first subassembly 10 are bordered by an adjacent microelectronic element 12 at all four edges, as shown in FIG. 1A. The microelectronic elements 12 positioned at a first end 11, a second end 13, a third end 15 or a fourth end 17 of the wafer have at least one edge unencumbered by an additional microelectronic element. Although the edges are depicted in the drawings for clarity of illustration, in practice the edges may not be visible. Rather, at this stage, the edges or strips where adjacent microelectronic elements 12 contact one another are saw lanes or strips where the wafer can be cut without damaging the individual microelectronic elements. For instance, as shown in FIG. 1B, second edge 20′ of microelectronic element 12′ abuts first edge 18″ of microelectronic element 12″ and forms a saw lane 23. Similarly, throughout the wafer 10, saw lanes 23 are located at positions where microelectronic elements 12 abut one another. The first wafer/subassembly 10 may include any number of microelectronic elements 12 including as little as two or as many as is desirable

Each of the microelectronic elements 12 also includes a plurality of contacts 22 exposed at the respective front face 14 of the microelectronic element 12. Further, a trace 24 extends outwardly from each of the contacts 22 to a respective first, second, third or fourth edge 18, 20, 19, and 21 of the individual microelectronic element 12. For example, with reference to FIG. 1B, trace 24′ extends outwardly from contact 22′ towards the second edge 20′ of microelectronic element 12′. The trace 24′ extends to and contacts trace 24″, which extends outwardly from contact 22″. Thus, traces 24′ and 24″ meet at the attachment point of microelectronic elements 12′ and 12″ and may actually form a single trace extending between contact 22′ and contact 22′. However, it is not required that the traces actually contact one another. Similar structures may be included for all adjacent microelectronic elements 12. Once again, contacts 22, which are positioned at the respective ends of the first subassembly 10 do not have traces 24 that extend to an adjacent contact on a different microelectronic element, but rather these traces 24 simply extend to a respective end of the first assembly 10.

As shown in FIG. 2, to create a stacked assembly 30, the first subassembly 10 is positioned over a second wafer/subassembly 10A and third wafer/subassembly 10B. The second subassembly and third subassembly 10A, 10B are similarly constructed to the first subassembly 10 and thus like elements will be given similar character references unless otherwise specified. The stacked assembly 30 of FIG. 2 includes three individual wafers/subassemblies stacked one upon another, but in alternate embodiments the stacked assembly 30 may include less or more wafers/subassemblies positioned on top of each other.

As shown in FIG. 2, the microelectronic elements 12 of the first subassembly 10 are aligned with the microelectronic elements 12A of the second subassembly 10A and the microelectronic elements 12B of the third subassembly 10B. Thus, the respective first, second, third and fourth edges of each of the microelectronic elements 12, 12A, 12B of the respective subassemblies 10, 10A, 10B are also aligned along longitudinal axes. Therefore, the respective saw lanes 23, 23A and 23B of each of the subassemblies are also aligned with one another. The stacked assembly 30 consists of a plurality of microelectronic elements 12, 12A, 12B, oriented and aligned in various rows and columns.

To attach the individual subassemblies 10, 10A, 10B to one another, an adhesive layer 32 is positioned between the front face 14 of the first subassembly 10 and the rear face 16A of the second subassembly 10A. Similarly, an adhesive layer 33 is also positioned between the front face 14A of the second subassembly 10A and the rear face 16B of the third subassembly 10B. An additional adhesive layer 35 may also be disposed on the front face 14B of the third subassembly 10B so as to protect the contacts 22B and traces 24B of the third subassembly 10B. The adhesive layers 32, 33, 35 may be formed from an epoxy or the like.

Once assembled, the adhesive layers 32, 33, 35 are allowed to cure such that the respective subassemblies 10, 10A, 10B are adhered to one another and form stacked assembly 30, which includes a plurality of microelectronic elements 12, 12A, 12B stacked adjacent to and upon one another.

With reference to FIG. 3, next, a plurality of notches 46 may be cut into the stacked assembly 30. The notches 46 are preferably formed using a mechanical cutting instrument not shown in the figures. Examples of such a mechanical cutting instrument can be found in U.S. Pat. Nos. 6,646,289 and 6,972,480, the disclosures of which are hereby incorporated by reference herein. The notches 46 are cut from the stacked assembly 30 at locations that are proximate the respective first edges 18, 18A, 18B, second edges 20, 20A and 20B, third edges 19, 19A, 19B and fourth edges 21, 21A, 21B of the respective microelectronic elements 12, 12A, 12B of the various subassemblies 10, 10A, 10B. The notches 46 are formed by cutting gaps 47 at the saw lanes 23, 23A and 23B. Since the saw lanes 23, 23A and 23B of each of the subassemblies 10, 10A 10B are aligned throughout the stacked assembly 30, a single cut may be used to form the gaps 47 between multiple subassemblies. Preferably, the notches 46 do not extend entirely through the stacked assembly 30. For instance, as shown in FIG. 3, the microelectronic elements 12 of the first subassembly 10 remain attached to each other as the various notches 46 do not extend entirely through the first subassembly. However, the notches 46 do extend far enough so as to intersect the traces 24 of the first subassembly 10 that extend between contacts 22 exposed at adjacent microelectronic elements 12. Similarly, the notches 46 dissect not only the various adhesive layers 32, 33, 35 interconnecting the subassemblies 10, 10A, 10B but also adjacent microelectronic elements 12A, 12B and respective traces 24, 24A, 24B of each subassembly. Although the notches 46 are illustrated having inclined side walls 48, 50, the side walls may also be straight.

For example, notch 46A of FIG. 3 intersects microelectronic element 52 and microelectronic element 54 of second subassembly 10A. The notch 46A intersects the two microelectronic elements 52, 54 such that the various edges of each of the microelectronic elements, which were previously attached to one another and formed saw lane 23 are separated by a gap 47. The gap 47 created by the notch 46A exposes the traces 56 and 58 adjacent the notch 46A. A similar structure is preferably included for all of the edges of the various microelectronic elements throughout the stacked assembly 30. The exposed traces 24, 24A, 24B form contact surfaces for each of the microelectronic elements 12, 12A, 12B. Of course, the first edge 60 and second edge 62 of the stacked assembly 30 does not have to be mechanically cut because the traces that extend toward these respective edges are already exposed. Although not shown in FIG. 3, the first and second edge 60, 62 may also be mechanically cut so as to create a more symmetrical configuration. Similarly, the edges of the stacked assembly 30 not shown in the figures also do not have to be mechanically cut although it may be desirable.

Once the various notches 46 have been created in the stacked assembly 30, leads 66 may be formed on the inclined side walls 48, 50 of notches 46. The inclined side walls 48, 50 extend through at least part of the various first, second and third subassemblies, 10, 10A, 10B, that were created as a result of the notches 46, as shown in FIGS. 4A and 4B. The leads 66 may be formed by any suitable metal deposition technique, for example, a process that includes sputtering, three-dimensional lithography and electroplating. Additional processes may also be employed. One such process is disclosed in U.S. Pat. No. 5,716,759, the disclosure of which is hereby incorporated by reference herein. The leads 66 extend within the various notches 46, and establish electrical contact with the traces 24, 24A and 24B. Preferably the leads 66 extend past the inclined side walls 48, 50 of notches 46 and are exposed at a first surface 70 of the adhesive layer 35 positioned below the third subassembly 10B. Therefore, the leads 66 include ends 75 remote from notches 46 and exposed on the surface of adhesive layer 35. Pads or solder bumps 74 may be formed at the ends 75 of the leads 66. Each lead 66 is in contact with three traces 24, 24A, 24B as a result of the traces being aligned and exposed at a respective inclined side wall 48 or 50. However, the leads 66 may be in electrical connection with only one or two of the traces 24, 24A, 24B at a respective inclined side wall 48 or 50. Such an orientation may be as a result of the positioning of the traces 24, 24A, 24B in different planes that are into and out of the page as viewed by the reader. For example, trace 24 illustrated in FIG. 4B may be offset from trace 24A so that trace 24 is closer to the reader if viewing in a three-dimensional orientation. The lead 66, which is aligned with trace 24, is also offset from trace 24A and not in contact with trace 24A. So although in a two-dimensional view, the traces 24, 24A may appear to be attached to lead 66 in FIG. 4B, only one may be actually attached to the lead.

As shown in FIG. 5, after the notches 46 and various conductive elements including leads 66 are formed in the stacked assembly 30, individual packages 80 may be created by mechanically cutting through the wafer 10 of microelectronic elements 12 of the first subassembly 10. The microelectronic elements 12 of the first subassembly 10 are cut at locations that are proximate the notches 46 such that the notches 46 are allowed to extend entirely through the stacked assembly 30. Once the cuts have been performed, a plurality of stacked individual units 80 are created, with each stacked individual unit 80 containing a plurality of microelectronic elements stacked one upon another. The stacked individual units 80 may be electrically connected to a microelectronic element such as a substrate 83, circuit board or circuit panel via the solder bumps 74, as shown in FIG. 5.

The stacked individual unit 80 may be incorporated into microprocessors and RF units among other assemblies but may be particularly adaptable for Flash Memory and DRAM units.

In an alternate embodiment, as shown in FIG. 6, the stacked assembly 130 may include an additional substrate such as packaging layer 180. Stacked assembly 130 is similarly constructed to stacked assembly 30 discussed previously with regard to FIGS. 1-5 and includes most if not all of the same features discussed with regard to stacked assembly 30. In addition, stacked assembly 130 may be constructed following steps previously discussed with regard to stacked assembly 30. The only addition to stacked assembly 130 as compared to stacked assembly 30 is that during the manufacture of the stacked assembly 130 and preferably prior to creating notches in the stacked assembly 130, a packaging layer 180 is positioned below compliant layer 135. The packaging layer 180 is preferably formed of glass, silicon or a similar material. Once the packaging layer 180 has been positioned adjacent to the adhesive layer 135, a plurality of notches 146 are formed using a cutting instrument, as discussed with regard to stacked assembly 30. This exposes traces 124, 124A, 124B at the inclined side walls, 148, 150 of the notches 146. Further, a plurality of leads 166 may then be created on the inclined side walls 148, 150 and be placed in electrical contact with the various traces 124, 124A, 124B exposed at the inclined side walls, 148, 150 of the notches 146 as discussed with regard to stacked assembly 30. The various leads 166 preferably extend beyond the notches 146 and onto a front surface 182 of the packaging layer 180. Exposed ends 175 of the leads 166 may include pads or solder bumps 174. Although not shown in FIG. 6, once the various notches and conductive elements have been formed, the notches may be extended through the row of microelectronic elements 112 of the first subassembly 110 so as to create individual stacked units 180.

In an alternate embodiment, as shown in FIGS. 7-22, the stacked assembly 230 may include an additional substrate such as packaging layer 201. Stacked assembly 230 is similarly constructed to stacked assemblies 30 and 130 discussed previously with regard to FIGS. 1-7, except that the assembly starts with substrate layer 201, and includes many of the same features discussed with regard to stacked assembly 30 and 130. In addition, stacked assembly 230 may be constructed following steps previously discussed with regard to stacked assemblies 30 and 230.

As shown in FIGS. 7A-7C, a portion of a first wafer or subassembly 210 includes a plurality of microelectronic elements 212, each positioned side by side and adjacent to one another. The first wafer or subassembly 210 preferably includes numerous rows of microelectronic elements 212 aligned along an X-axis and a Y-axis. The microelectronic elements are formed integral with one another using conventional semiconductor process techniques. It should be apparent that the subassembly 210 may be a portion of a wafer and that the various components are replicated repeatedly over the extent of the wafer. The FIGS. 7A-7C illustrate that the subassembly may have additional elements attached thereto and may be in the shape of a circular wafer.

Each microelectronic element 212 includes a front face 214 and an oppositely-facing rear face 216. The microelectronic elements 212 also include first edges 218, second edges 220, third edges 219 and fourth edges 221, all of which extend from the front faces 214 to the rear faces 216 of the microelectronic elements 212. As shown in FIGS. 7A-7C, a first edge 218 of one microelectronic element 212 is attached to a second edge 220 of a second and adjacent microelectronic element 212. Similarly, a third edge 219 of one microelectronic element 212 is attached to a fourth edge 221 of an adjacent microelectronic element. Thus, the microelectronic elements 212 positioned within the middle of the first subassembly 210 are bordered by an adjacent microelectronic element 212 at all four edges, as shown in FIG. 7A. The microelectronic elements 212 positioned at a first end 211, a second end 213, a third end 215 or a fourth end 217 of the wafer have at least one edge unencumbered by an additional microelectronic element. Although the edges are depicted in the drawings for clarity of illustration, in practice the edges may not be visible. Rather, at this stage the edges or strips where adjacent microelectronic elements 212 contact one another are saw lanes or strips where the wafer can be cut without damaging the individual microelectronic elements. For instance, as shown in FIG. 7B, second edge 220′ of microelectronic element 212′ abuts first edge 218″ of microelectronic element 212″ and forms a saw lane 223. Similarly, throughout the wafer 210, saw lanes 223 are located at positions where microelectronic elements 212 abut one another. The first wafer/subassembly 210 may include any number of microelectronic elements 212 including as little as two or as many as are desirable.

Each of the microelectronic elements 212 also includes a plurality of contacts 222 exposed at the respective front face 14 of the microelectronic element 212 best seen in FIG. 7C. Further, a trace 224 extends outwardly from each of the contacts 222 to respective edges 218, 220, 219, and 221 of the individual microelectronic element 212. The traces 224 may meet at the attachment point of microelectronic elements 212′ and 212″ and may actually form a single trace extending between contact 222′ and contact 222″. However, it is not required that the traces actually contact one another. Similar structures may be included for all adjacent microelectronic elements 212. Once again, contacts 222, which are positioned at the respective ends of the first subassembly 210 do not have traces 224 that extend to an adjacent contact on a different microelectronic element, but rather these traces 224 simply extend to a respective end of the first assembly 210.

In contrast to the embodiments discussed in connection with FIGS. 1-6, the embodiment of FIGS. 7-22 is shown constructed in stacked fashion from the substrate upwards. Consequently, many of the various components and processes are depicted in inverted fashion related to the earlier figures.

A packaging support wafer or layer 201 with substrate 202 for the stacked assembly of this embodiment is shown in FIG. 8. The substrate 202 is preferably formed of glass, silicon or a similar material that provides sufficient mechanical strength to support and reinforce the subsequent layers of the stacked assembly. For this reason, the substrate 202 may be thicker than the subsequent layers. The substrate layer 202 material may also be thinned or even removed during later process steps by etching or mechanically polishing when support is no longer needed. The substrate has a lower surface 205 and an upper surface 206 and extends to a leftward side 203 and rightward surface 204. Depicted in FIG. 9 are a plurality of relief cavities 208 and 208′ created in the upper surface 206. These cavities 208 are aligned with the anticipated positions of saw lanes for severing the stacked packages. The cavities 208, 208′ are created by mechanical cutting instruments as described above for the stacked assemblies 30 and 130. The relief cavities 208, 208′ function as a stress relief to prevent fracture of the stacked assemblies due to notching of the substrate 202 during subsequent operations. Consequently, the cavities 208 are preferably formed with corner radii to alleviate stress concentrations. After forming the cavities 208, 208′ an adhesive layer 209 is applied to the upper surface 206 and the cavities 208, 208′ as shown in FIG. 10. Preferably the adhesive layer has a thickness over the upper surface 206 of 2.5-4.0 micrometers.

As shown in FIG. 11, to create a stacked assembly, the first subassembly 212 is positioned over the substrate layer 201. As depicted, the contacts 222, 222′ and traces 224, 224′ are aligned with the respective cavities 208, 208′ and thus saw lanes 218 and 222. The active lower surface 214 and the traces 224 and 224′ are applied to the adhesive layer 209 of the substrate layer 201 and the adhesive is cured. The subassembly 210, including the traces 224 and 224′ are bonded to and supported by the substrate layer 201.

If desired, the upper surface 216 of the subassembly 210 may be thinned to create a new surface 216′ and reduce the height of the subassembly as shown in FIG. 12. Preferably the reduced height of the subassembly is 22.4-25.4 micrometers if a compact stacked package is desired.

With reference to FIG. 13, next, a plurality of initial notches 240, 240′ may be formed into the subassembly 210 to expose the traces 224, 224′. The notches 240, 240′ are preferably formed using non-mechanical techniques such as selective chemical etching in order to preserve the delicate traces 240, 240′. The traces 240, 240′ are adhered to and supported by the adhesive 209 of the substrate 201 during this step. The initial notches 240, 240′ are aligned with the contacts 222, 222′, the traces 224, 224′ the cavities 208, 208′ and saw lanes 218 and 222. The profile of the initial notches 40, 41 is configured to provide clearance for later notches as will be described.

After forming initial notches 240, 240′, an adhesive layer 243 is applied to the upper surface 216 or 216′ and the initial notches 40, 40′, as shown in FIG. 14. Preferably the adhesive layer has a thickness over the upper surface 216 or 216′ of approximately 2.5-4.0 micrometers.

As shown in FIGS. 15 and 16, second, third and fourth subassemblies, designated 210A, 210B and 210C respectively, are aligned with subassembly 210, stacked and laminated sequentially upward from subassembly 210 and substrate layer 201. The same sequence of steps earlier followed to laminate subassembly 210 to substrate 201 is used to laminate each of subassemblies 210A, 210B and 210C. The steps including alignment, lamination, curing, thinning, creation of initial notches and application of adhesive are followed sequentially for each step to create the stacked assembly 230. Thus microelectronic elements 212 of the first subassembly 210 are aligned with the microelectronic elements 212A of the second subassembly 210A, the microelectronic elements 212B of the third subassembly 210B, and the microelectronic elements 212C of the third subassembly 210C. Therefore, the initial notches 240, 240′, 240A, 240A′, 240B, 240B′, 240C, 240C′, are respectively aligned with the contacts 222, 222′, 222A, 222A′, 222B, 222B′, 222C, 222C′, the traces 224, 224′, 224A, 224A′, 224B, 224B′, 224C, 224C′, the cavities 208, 208′ and the saw lanes 218 and 222. In summary, the stacked assembly 230 consists of a plurality of stacked and adhered microelectronic elements 12, 12A, 12B, 12C oriented and aligned in various rows and columns.

The notches 246 are cut from the stacked assembly 230 at locations that are proximate the respective first edges 218, 218A, 218B, and 218C, second edges 220, 220A, 220B and 220C, third edges 219, 219A, 219B, 219C and fourth edges 221, 221A, 221B, 221C of the respective microelectronic elements 12, 12A, 12B, 12C of the various subassemblies 10, 10A, 10B, 10C. The notches 246, 247 are formed at the saw lanes 220, 218 by the methods described for the earlier embodiments. As seen in FIG. 17, one notable difference from the earlier embodiments is that the plurality of notches 246 are cut through the adhesive layers 243, 243A, 243B, 243C. Preferably, the notches 246 do not extend entirely through the stacked assembly 230 but rather extend only partially into the relief cavities 208, 208′. Thus the substrate 202 remains intact to connect the stacked microelectronic elements and is protected from cracking because the adhesive 209 rather that the substrate is cut. Although the notches 246 are illustrated having inclined side walls 248, 250, the side walls may also be straight.

The stacked assembly 230 of FIG. 17 includes four individual wafers/subassemblies stacked one upon another, but in alternate embodiments the stacked assembly 230 may include less or more wafers/subassemblies positioned on top of each other. Also shown in FIG. 17 is an optional thinning of the substrate 202 which may be accomplished by mechanical polishing or etching. This step may be performed between various steps in the process, preferably after formation of the notches 246.

Once the various notches 246 have been created in the stacked assembly 230, leads 266 may be formed on the inclined side walls 248, 250 of notches 246. The inclined side walls 248, 250 extend through at least part of the various first, second, third and fourth subassemblies 210, 210A, 210B, 210C that were created as a result of the notches 246, as shown in FIGS. 17 and 18. The leads 266 may be formed by any suitable metal deposition technique as described for the previous embodiments. The leads 266 extend within the various notches 246, and establish electrical contact with the traces 224, 224A, 224B and 224C.

Preferably the leads 266 extend past the inclined side walls 248, 250 of notches 246 and are adhered to the adhesive layer 243C on the upper surface 216C′ of the third subassembly 210C. Therefore, the leads 266 include ends 275 remote from notches 246 and exposed on the surface of adhesive layer 243C.

Each lead 266 is in contact with four traces 224, 224A, 224B, 224C as a result of the traces being aligned and exposed at respective inclined side walls 248 or 250. However, the leads 266 may be in electrical connection with less than four of the traces 224, 224A, 224B, 24C at a respective inclined side wall 48 or 50. Such an orientation may be as a result of the positioning of the traces 224, 224A, 224B, 224C in different planes that are into and out of the page as viewed by the reader as discussed for the previous embodiments.

Pads or solder bumps may be formed at the ends 275 of the leads 266. To that end, solder mask 277 may be patterned over the surface of adhesive layer 216C and leads 266 as shown in FIG. 19 for the attachment of wires or solder bumps.

In another optional embodiment shown in FIG. 20, leads 266 may be extended to the bottom surface of the substrate 202. The leads 266 extend past the inclined side walls 248, 250 of notches 246 and enter the adhesive layer 209 within the relief cavity 208 positioned below the first subassembly 210. Upon further thinning of the substrate 202, the bottom of leads 266 are exposed and the leads may be extended by the methods previously discussed to create bottom leads 286. Solder mask 227 may be patterned over the bottom surface of substrate 202 for the attachment of wires or solder bumps to allow the formation of pads or bumps at the ends 288.

A particular advantage of this arrangement is that either stacked assemblies 230 or individual packages may in turn be stacked and electrically interconnected, one upon the other by aligning and connecting using, for instance solder bumps, the respective top ends 275 and bottom ends 288. In the example shown, the top ends 275 and bottom ends 288 to be connected are align in an appropriate pattern in the x-y plane to allow interconnection.

Because the leads 266 allow testing probes to access the elements, defective subassembly layers may be detected and isolated to allow sorting and rework. Higher-level integration as well as wafer level rework is facilitated by the ability to stack assemblies 230. Thus, leads disposed at a bottom surface of a unit as illustrated in FIG. 20 may be connected to leads provided at a top surface of an adjacent unit through conductive masses, e.g., spheres or bumps of conductive material, e.g., solder. While having a greater overall thickness, elements from such stacked stack assemblies are functionally repaired to be equivalent to a non-defective stack assembly 230 and the value of the functioning layers 210 may be economically recovered by wafer level rework.

As shown in FIG. 21, after the notches 246 and various conductive elements including leads 266 are formed in the stacked assembly 230, individual packages 280 may be created by mechanically cutting through the leads 266, the adhesive 209 and the substrate 202, to sever the packages. The cut are aligned with dicing lanes 218 and 220 at locations that are proximate the notches 246 such that the notches 246 are allowed to extend entirely through the stacked assembly 230. Once the cuts have been performed, a plurality of stacked individual elements 280 are created, with each stacked individual unit 280 containing a plurality of microelectronic elements stacked one upon another. The stacked individual units 280 as shown in FIG. 22 may be electrically connected to a microelectronic element such as a substrate, circuit board or circuit panel via wire bonding or via pads 275 or the solder bumps 274, as shown in FIG. 23.

In a particular example (FIG. 20A), three stacked assemblies 230 of the type shown in FIG. 20 or FIG. 21 may be stacked and interconnected. Bond wires 2202, 2202′, 2202″ connecting lands 2204, 2204′ and 2204″ of the stacked assemblies provide interconnection to terminals 2206 of a circuit panel 2210. The bond wires may be arranged to connect lands of adjacent levels as shown in FIG. 20A or each bond wire may directly connect a stacked assembly to the circuit panel. Alternatively, some of the bond wires connected to a particular stacked assembly may be connected to another stacked assembly which is not adjacent to the particular stacked assembly.

As apparent in FIG. 20A, a face 2220″ of a stacked assembly 230″ and a land 2204″ thereon extends beyond a face 2220′ and an edge 2222′ of stacked assembly 230′ and a land 2204′ thereon, thus permitting the lands 2204′ and 2204″ to be interconnected using bond wire 2202′. Similarly, a face 2220′ of the stacked assembly 230′ and the land 2204′ thereon extends beyond a face 2220 and an edge 2222 of stacked assembly 230 and a land 2204 thereon, thus permitting the lands 2204′ and 2204 to be interconnected using bond wire 2202.

The embodiments (FIGS. 7-23) described above result in thin elements 280 produced by wafer level packaging. Because the individual layers can be fabricated with thickness of approximately 25 micrometers, a total die package using a 30 micrometer substrate can be no less than 155 micrometers thick. As described, the substrate can be further thinned to reduce the package thickness to less than 125 micrometers.

In the method of fabricating a stacked package as described above (FIGS. 7-23), notches 246 are formed in the stacked assembly 230 (FIG. 17). The notches typically extend along edges of each microelectronic element 212, 212′ aligned with saw lanes 218, 220, etc., such that a series of traces 224 (FIG. 7C) of each microelectronic element are exposed within the notches at the edges. The notches may extend the entire length of the respective saw lanes of the stacked assembly 230 or may be a series of openings each extending a part of the length of the respective saw lane to which the opening is aligned. As depicted in FIG. 7C, all of the traces 224 extending from contacts 222″ of microelectronic element 212 and all of the traces 224 extending from contacts 222′ of microelectronic element 212′ may be exposed within one notch 246 (FIG. 17). Leads 266 (FIG. 18) may then be formed by depositing a primary metal layer, e.g., by sputtering, electroless deposition, etc., along edges of the subassemblies 210 exposed within the notches. The primary metal layer can then be photolithographically patterned into separate leads, followed by electroplating to increase the thickness of leads and if desired, form leads having multiple different metal layers.

Referring to FIG. 24, in a variation of the above embodiment, after forming the stacked assembly 230 (FIGS. 16-17), instead of forming notches which expose all of the traces 224 aligned with the saw lanes 218, 220 (FIG. 7C) of each microelectronic element 212, 212′, etc., openings 228, 228′, 228″ are formed in alignment with the saw lanes 218, 220, etc. However, unlike the notches 246 (FIG. 17) in the above-described embodiment, each of the openings 228, 228′, 228″, etc., exposes no more than a single trace 224, 224′, 224″ of each respective microelectronic element. Typically, traces 224 connected to contacts of adjacent microelectronic elements 212, 212′ are exposed within an opening 228. Similarly, traces 224′ connected to contacts of the adjacent microelectronic elements are exposed within another 228′ of the openings, and traces 224 connected to contacts of the adjacent microelectronic elements are exposed within another 228″ of the openings. In the stacked assembly 230, respective traces 224 connected to microelectronic elements of the stacked subassemblies may be exposed within a single opening, but no more than one trace of each microelectronic element is exposed within each opening.

To form leads 266 (FIG. 18) connected to individual ones of the traces 224, 224′ and 224″, etc., all openings 228, 228′, 228″, etc., in the stacked assembly can be simultaneously filled with a conductor to form conductive vias connected to single traces of each microelectronic element. For example, the openings can be filled with a metal to form conductive vias by depositing a primary metal, e.g., by sputtering or electroless deposition, and then electroplating the resulting structure. Metal remaining from the electroplating step which lies above the surface of the exposed adhesive or dielectric layer 243C. (FIG. 18) can be removed, leaving surfaces of individual conductive vias exposed in each opening 228. Alternatively, the resulting metal layer overlying the uppermost adhesive layer 243C can be patterned by photolithography into individual leads 266 (FIG. 18) extending from the vias over layer 243C. Conductive bumps may then be formed at ends of the leads, as shown and described above with reference to FIG. 23.

Reference is now made to FIGS. 25A and 25B, which are illustrations of apparatus employed in the manufacture of assemblies of the types discussed herein. As seen in FIGS. 25A and 25B, a conventional wafer fabrication facility 680 provides complete wafers 681, of the type partially shown in FIGS. 1A and 1B. Individual wafers 682 are bonded on their active surfaces to protective layers 683 by bonding apparatus 685, preferably having facilities for rotation of the wafer 682, the layer 683 and epoxy so as to obtain even distribution of the epoxy.

The bonded wafer 686 is thinned at its non-active surface as by grinding apparatus 684 using an abrasive 687. The wafer is then etched at its non-active surface, preferably by photolithography, such as by using conventional spin-coated photoresist, using a mask exposure machine 692 for the exposure of light sensitive photoresist 690 through the mask 691 and later etching the silicon in a bath 693 using solution 699. The etched wafer is bonded on the non-active side to protective layer 686 by bonding apparatus 694, which may be essentially the same as apparatus 685, to produce a doubly bonded wafer sandwich. The wafer may then by bonded to a second or more wafers.

Notching apparatus 695 partially cuts the bonded wafers in a method of forming a stacked package as described above with reference to FIGS. 1-6. The notched wafers are then subjected to anti-corrosion treatment in a bath 696, containing a chromating solution 698. Alternatively, a chemical etching apparatus (not shown) may be used to form notches exposing one or more traces or openings exposing single traces of respective microelectronic elements in accordance with the methods of fabrication described above with respect to FIGS. 7-24.

Conductive layer deposition apparatus 700, which operates by vacuum deposition techniques, is employed to produce a conductive layer on one or more surfaces of each die of the wafers. The conductive layer deposition apparatus 700 may be employed prior to the two wafers being assembled together. Configuration of the contact strips or lead bridges is carried out preferably by using conventional electro-deposited photoresist 701. The photoresist 701 is applied to the stacked wafers 707 in a photoresist bath assembly 702. The photoresist 701 is preferably light configured by a UV exposure system 704, which may be identical to system 692, using a mask 705 to define suitable etching patterns. The photoresist is then developed in a development bath 706, and then the wafer is etched in a metal solution 708 located in an etching bath 710, thus providing a conductor configuration.

The exposed conductive strips are then plated, preferably by electroless plating apparatus 712. The stacked wafers are then diced into individual prepackaged integrated devices. Preferably the dicing blade 714 should be a diamond resinoid blade of thickness 4-12 mils, which corresponds to the thickness of the saw lanes.

Referring to FIG. 26, a stacked assembly 280 (FIG. 22) is shown having a rear face 2602 attached, e.g., by way of an adhesive (not shown), to an interconnection element 2610 or circuit panel. Bond wires 2604 electrically connect ends 2668 of leads 2666 to contacts 2606 on an inner face 2601 of an interconnection element 2610. In turn, the contacts 2606 are connected by way of vias 2608 to conductive bumps or balls 2612, e.g., solder balls exposed at an outer face 2611 of the interconnection element. As further shown in FIG. 26, a microelectronic element, e.g., a semiconductor chip, may be connected to leads 2666 extending above a front face 2622 of a microelectronic element 210 of the stacked assembly 280 through conductive masses 2624, e.g., solder balls, among others. In a particular embodiment, microelectronic elements 210 included in the stacked assembly include memory devices, including, without limitation, dynamic random access memories (“DRAMs”), static random access memories (“SRAMs”), erasable programmable read only memories (“EPROMs”), e.g., such memories which can be erased via exposure to radiation or which can be erased and reprogrammed via electrical means, or flash memory, which is a form of nonvolatile random access memory in which data can be stored, altered and overwritten without having to reprogram the chip.

In a particular example, the chip 2620 includes a processor, e.g., microprocessor or microcontroller element, among others, the processor capable of accessing and executing a program in connection with use of the memory resources contained in the stacked assembly 280. In another example, the chip 2620 may contain circuitry which matches that of one or more of the microelectronic elements 210 in function or circuitry. In such case, chip 2620 can serve as a replacement unit connected by way of leads 2666 to other microelectronic elements 210, the chip 2620 connected by way of bond wires 2604 to the interconnection element. To set up the chip 2620 as a repair-replacement unit for an assembly having a defective microelectronic element 210, leads extending from that defective microelectronic element can be electrically disconnected from contacts at the front face 2622, e.g., by mechanical or laser techniques. Alternatively, electrically fusible elements (e.g., electrical fuses or antifuses) of the chip 2620 or of the defective element 210 can be activated. The repair chip 2620 can be electrically connected in place of the defective chip of the stacked assembly.

FIG. 27 illustrates a variation of the embodiment illustrated in FIG. 26, wherein a chip 2720 is mounted with a front face 2722 thereof facing away from the front face 2622 of the adjacent microelectronic element 210. Bond wires 2704 connect pads 2716 of the chip to contacts 2706 of the interconnection element. In a further variation shown in FIG. 28, bond wires 2804 connected to the pads 2704 of the chip 2720 are connected to exposed contacts 2806 on the stacked assembly. The exposed contacts 2806 may be connected to one or more of the microelectronic elements of the stacked assembly by way of leads 2666. Alternatively, or in addition thereto, the exposed contacts 2806 may be connected to the interconnection element by way of other bond wires 2814.

In another variation shown in FIG. 29, ends 2968 of leads 2966 exposed at a rear face 2902 of a stacked assembly 230 (as described above with reference to FIG. 20) are connected to contacts 2906 of the interconnection element 2910 by way of conductive masses, e.g., solder balls, among others. FIG. 30 illustrates a variation of the embodiment shown in FIG. 29, in which a chip 2720 mounted to the front face 3001 of the stacked assembly is electrically connected directly to the interconnection element 3010 by way of bond wires 3004 which extend from pads on the chip 2720 to contacts 3006 of the interconnection element. In another variation shown in FIG. 31, a chip 2620 is flip-chip mounted to ends of leads 2666 or other contacts exposed at the front face 3001 of the stacked assembly. In a further variation shown in FIG. 32, a stacked assembly 280 is flip-chip mounted to an interconnection element 2610, with the front face 3201 of the stacked assembly confronting a front face 2601 of the interconnection element.

Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims. 

1. A method of manufacturing a stacked microelectronic package comprising the steps of: (a) forming a first element including a first wafer and a second wafer overlying the first wafer, each of the first and second wafers including a plurality of microelectronic elements, a plurality of first saw lanes extending in a first direction and a plurality of second saw lanes extending in a second direction transverse to the first direction, a given first saw lane of the second wafer being aligned with and positioned above a given saw lane of the first wafer, wherein the plurality of first saw lanes and the plurality of second saw lanes extend between adjacent ones of the microelectronic elements of each wafer, at least one microelectronic element has a plurality of contacts exposed at a face of the first wafer or of the second wafer and a plurality of metal traces electrically connected with respective ones of the contacts and extending toward the aligned first saw lanes, and the first element further includes an insulating region extending in the first direction and aligned with the aligned first saw lanes; (b) forming at least one opening in the insulating region in alignment with the aligned first saw lanes, each at least one opening exposing no more than a single trace of the plurality of traces of the at least one microelectronic element; (c) forming a lead within the at least one opening, the lead being electrically connected to no more than a single trace of the at least one microelectronic element; and (d) severing the first and the second wafers along the aligned first saw lanes and through the insulating regions into a plurality of assemblies, each assembly including a plurality of stacked microelectronic elements and exposed leads.
 2. The method as claimed in claim 1, wherein the at least one opening exposes no more than a single trace of a first microelectronic element of the first wafer and no more than a single trace of a second microelectronic element of the second wafer.
 3. The method as claimed in claim 1, wherein the leads include first ends overlying a face of one of the first and the second wafers.
 4. The method as claimed in claim 3, wherein the first ends of the leads include conductive bumps.
 5. The method as claimed in claim 1, wherein the at least one opening includes a plurality of openings in alignment with the aligned first saw lanes and spaced apart in the first direction, each of the plurality of openings being insulated from each other opening of the plurality of openings.
 6. The method as claimed in claim 5, wherein step (c) includes forming conductors, each conductor contacting an exposed trace within one of the plurality of openings, and step (d) includes severing the conductors along the aligned first saw lane, such that the leads include severed portions of the conductors.
 7. The method as claimed in claim 6, wherein the forming of the conductors includes depositing a conductive material within the openings.
 8. The method as claimed in claim 6, wherein the forming of the conductors includes filling the openings with a metal. 